Generally, dynamic random access memories (DRAMs) have a large number of memory cells each including a metal-oxide-semiconductor field effect transistor (MOSFET) and a capacitor. Conventional fabrication of DRAM devices typically have two separate contact patterning processes. One is for forming bit line contacts and the other is for forming capacitor node contacts.
In this conventional method, the distance from the capacitor node to substrate is relatively large, more particularly, for the structure of capacitor-over-bitline DRAMs. Consequently, the node contact hole has a relatively high aspect ratio. As is well known, forming a contact hole with high aspect ratio is relatively difficult using standard photolithography and etching techniques, often requiring overetching to ensure that the contact hole is complete. This overetching may cause short-circuit defects. In addition, filling the high aspect ratio contact hole with a conductive material can also be difficult, thereby increasing the risk of open-circuit defects. Thus, there is a need for a method to form contacts in a high density integrated circuit without the problems associated with high aspect ratio contact holes.